1. Field of the Invention
The invention relates to the field of manufacture of microelectronics fabrications. More particularly, the invention relates to the field of formation of via holes for low resistance electrical contacts within semiconductor integrated circuit microelectronics fabrications.
2. Description of the Related Art
The manufacture of microelectronics fabrications employing semiconductor and conductor elements requires that electrical contacts be formed between and among the several conductive and semiconductive regions and patterned layers. Such electrical contacts generally must be made so that they are ohmic in nature, i.e., they obey Ohm""s law of proportionality of electric current to voltage. In addition, electrical contacts should be made reliably and with low intrinsic resistance without significant added contribution to the electrical resistances and impedances of the circuits components and connections comprising the microelectronics fabrications. While there is generally no particular difficulty meeting these requirements for metal-to-metal contacts, more complex interactions may arise when forming contacts at interfaces between metal and semiconductor layers. For example, electronic states at the interface may exist, particularly in the semiconductor portion, which may trap charges and lead to formation of interfacial potential differences which may cause apparent changes in electrical resistance, particularly in the semiconductor material. Another effect which may cause changes in electrical resistance at the contact is the possibility of chemical reaction between the metal and semiconductor materials, which may cause formation of species with intrinsically higher electrical resistance than either the metal or the semiconductor themselves.
In complex microelectronics fabrications, the electrical contacts may be required to to be formed to and/or through intermediate conductor layers separated from the other conductor layers below and/or above by the intervening dielectric layers. In these instances, the geometry of the actual contact is different from that which is afforded when electrical contacts are formed between conductor layers separated by a dielectric layer. A contact via bole formed in a dielectric layer and terminating at a conductor contact layer affords the complete area of the contact hole at the conductor layer for this purpose, whereas in the latter case of an intermediate conductor contact layer the electrical contact formed by a through-going or penetrating via contact hole, the actual contact area will be limited to the thickness of the contact layer exposed at the periphery of the penetrating contact via hole.
In microelectronics fabrications, contact via holes formed within a dielectric layer are generally patterned by chemical subtractive etch methods using a photoresist etch mask to define the contact via hole pattern. A dry etching method is commonly employed for silicon containing dielectric layers wherein plasma activated fluorine containing gases react with the silicon containing dielectric material to form volatile silicon-fluorine compounds which leave no residue in the contact via holes. While such methods arc generally satisfactory, there may be side reactions leading to the formation of solid non-conductive residual materials such as carbon-fluorine containing polymers in the etched via hole which may interfere with subsequent electrical contact. After etching of the contact via holes is complete, the photoresist mask must be removed, which may constitute an additional source of residual polymer material left within the etched via.
It is common practice in plasma etching of contact via holes in silicon containing dielectric layers to include an oxidation post-etch treatment (PET) step to minimize the residual polymer material left within the contact via hole. An oxidizing gas is admitted after the via etching to react with any polymer residues. This method is not without problems in forming contact via holes with satisfactory contact resistances. For example, oxidizing environments may form poorly conducting oxide compounds which may interfere with electrical contact within the via contact hole. The oxidizing gas may not react sufficiently to remove the polymer or other foreign material from the contact hole.
It is therefore towards the goal of forming through dielectric layers within microelectronics fabrications a plurality of etched via holes with low electrical resistance contacts that the present invention is generally directed.
Various methods and materials have been disclosed with respect to dry etching of contact via holes and forming low and reproducible contact resistances. For example, Barnes et al., in U.S. Pat. No. 5,505,816, disclose a method for selectively etching silicon dioxide layers in a plasma formed from various gases including oxygen, fluorine compounds such as CF4 and NF3, N2 and H2, to form volatile products. The process is selective with respect to silicon nitride and polysilicon being etched more slowly.
Further, Carr et al., in U.S. Pat. No. 5,167,762, disclose a method for forming an etched hole through an oxide layer superposed over a polysilicon layer employing a plasma formed in a gas mixture including O2, He, C12 and NF3 for the first portion of the etching process, and completing the etching with a gas mixture containing NF3 and HBr to insure complete removal of the polysilicide formed within the etched hole during the first part of the process.
Still further, Cathey, in U.S. Pat. No. 5,314,578, discloses a method for etching a plurality of contact via holes through a silicon dioxide layer to an underlying silicon or metal silicide conductive layer. The method employs a carbon containing etchant protective material as the patterned etching mask and a carbon-free chemical etchant system containing halogens to effect the etching of the contact via holes. A polyhalocarbon polymer coating is formed as a protective layer byproduct of the etching reaction.
Yet still further, Imai et al., in U.S. Pat. No. 5,716,494 and U. S. Pat. No. 5,767.021, disclose a method employing an interhalogen compound gas to suppress film formation during dry etching of a silicon dioxide layer. The interhalogen compound gas is XeF2. Addition of interhalogen compound gases can also be used to suppress deposition of reaction products during chemical vapor deposition (CVD) procedures.
Still further yet, Butterbaugh et al., in U.S. Pat. No. 5,716,495, disclose a method for removing oxide and other contaminant layers from silicon wafer surfaces while minimizing loss of a desired film from the wafer surface. The method employs a fluorine-containing gas which is passed over the wafer surface whilst being irradiated with ultraviolet radiation to bring about the selective removal of oxide and other contaminant layers. The absence of water, hydrogen, hydrogen fluoride and hydrogen-containing organics is essential to operation of the method.
Finally, Armacoast et al., in U.S. Pat. No. 5,767,017, disclose a method for selectively removing portions of a layer from the vertical surface of an object whilst not affecting the adjacent horizontal surface of the same body. The method employs a fluorocarbon containing etching gas within a high density plasma to effect the selective removal of vertical and corner regions of the layer. This is accomplished by the masking effect of a patterned sacrificial polymer layer formed by first plasma etching of the layer to produce the conformal carbonaceous polymer layer which is then selectively etched at the corners by a second plasma etching step. The corner and vertical regions of the masked layer can then be selectively etched away.
Desirable within the art of microelectronics fabrication are additional methods for forming contact via holes through dielectric layers within microelectronics fabrications to produce low resistance electrical contacts within those contact via holes. More particularly desirable are methods and materials for forming contact via holes employing dry etching methods which provide a plurality of low resistance electrical contacts to and through intermediate contact layers within multi-level dielectric and conductor layer structures within microelectronics fabrications.
It is towards the foregoing goals that the present invention is both generally and more specifically directed.
It is a first object of the present invention to provide a method for forming within a dielectric layer formed over a series of multi-level contact layers upon a substrate within a microelectronics fabrication a series of via holes formed to access said contact layers employing selective etching of the dielectric layer.
It is a second object of the present invention to provide a method in accord with the first object of the present invention, where there is formed within a dielectric layer upon a substrate employed within an integrated circuit microelectronics fabrication over a series of multi-level contact layers at differing heights with respect to the substrate a series of via holes selectively etched within the dielectric layer to access the series of contact layers.
It is a third object of the present invention to provide a method in accord with the first object of the present invention or the second object of the present invention, where there is formed within a dielectric layer formed over a series of multi-level contact layers upon a substrate employed within a semiconductor integrated circuit microelectronics fabrication, said contact layers being of differing heights with respect to the substrate, a series of via holes selectively etched within the dielectric layers employing a reactive plasma etch method, accessing the contact layers to permit forming a series of low electrical resistance contacts therein, employing a patterned microelectronics conductor layer.
It is a fourth object of the present invention in accord with the first object of the present invention, the second object of the present invention and/or the third object of the present invention, where the method of the present invention is readily commercially implemented.
In accord with the objects of the present invention, there is provided by the present invention a method for forming within a dielectric layer over a series of contact layers formed upon a substrate employed within a microelectronics fabrication a series of via holes etched within the dielectric layer employing selective etching methods to access the contact layers wherein the electrical resistances of the series of electrical contacts formed to the contact layers are low and reproducible. To practice the method of the present invention, there is first provided a substrate employed within a microelectronics fabrication. There is then formed upon the substrate a series of patterned microelectronics multi-level contact layers and dielectric layers wherein the contact layers are of differing heights with respect to the substrate. There is then formed over the series of contact layers a dielectric layer. There is then formed upon the dielectric layer a photoresist etching mask pattern of a series of contact vias. There is then etched a series of contact via holes within the dielectric layer through the etching mask employing a plasma activated fluorine containing etching gas in a first etching step. At least one contact layer is penetrated through by the contact via holes. There is then employed oxygen and a fluorocarbon gas in a second etching step to complete the formation of the series of contact via holes. Subsequently there are formed electrical contacts through the contact via holes to the series of contact layers employing patterned conductor layers formed upon the dielectric layer to provide a series of low electrical resistance contacts.
The present invention may be employed where the microelectronics fabrication is an integrated circuit microelectronics fabrication. The method of the present invention does not discriminate with respect to the nature of the microelectronics fabrication within which there may be formed a series of contact via holes within a dielectric layer or layers. Thus, although the method of the present invention provides value when forming a series of contact via holes within a dielectric layer or layers formed within an integrated circuit microelectronics fabrication; the method of the present invention may also be employed when forming a series of contact via holes within a dielectric layer or layers within microelectronics fabrications including but not limited to semiconductor integrated circuit microelectronics fabrications, charge coupled device microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The present invention employs methods and materials which are known in the art of microelectronics fabrication but are employed in a sequence which constitutes a novel arrangement of operations to achieve the goal and objects of the present invention. Therefore the method of the present invention is readily commercially implemented.